URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [.] - Rev 26

Rev	Log message	Author	Age	Path
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2893d 18h	/.
5	Initial checkin, this time of the bench testing s/w.	dgisselq	2908d 22h	/.
4	Initial host software pack.	dgisselq	2908d 22h	/.
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2908d 22h	/.
2	Initial documentation/proposed specification. (I'm writing the spec as I'm building the core.)	dgisselq	2909d 16h	/.
1	The project and the structure was created	root	2909d 20h	/.