URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

Rev	Log message	Author	Age	Path
72	fix bug in interface to external data ram	simont	7927d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
62	fix bugs in instruction interface	simont	7932d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
54	cahnge interface to instruction rom	simont	7938d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
46	prepared header	simont	7955d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
37	added signals ack, stb and cyc	simont	7982d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
28	remove syn signal	simont	7993d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7993d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
19	combinatorial loop removed	simont	7996d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
17	fix some bugs	simont	7999d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
12	des1_r in alu port list	simont	8000d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v