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[/] [aemb/] [trunk/] [rtl] - Rev 65

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Rev Log message Author Age Path
28 Fixed simulation bug. sybreon 6287d 20h /aemb/trunk/rtl
27 Removed some unnecessary bubble control. sybreon 6288d 07h /aemb/trunk/rtl
26 Fixed minor synthesis bug. sybreon 6288d 07h /aemb/trunk/rtl
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v
sybreon 6288d 11h /aemb/trunk/rtl
24 Made minor performance optimisations. sybreon 6288d 21h /aemb/trunk/rtl
23 Fixed minor simulation bug. sybreon 6289d 13h /aemb/trunk/rtl
22 Added support for 8-bit and 16-bit data types. sybreon 6289d 13h /aemb/trunk/rtl
19 Added initial unified memory core. sybreon 6301d 22h /aemb/trunk/rtl
18 Moved testbench into /sim/verilog.
Simulation cleanups.
sybreon 6302d 15h /aemb/trunk/rtl
17 Cosmetic changes sybreon 6303d 19h /aemb/trunk/rtl

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