URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] - Rev 208

Rev	Log message	Author	Age	Path
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6110d 11h	/aemb/trunk/sim
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6111d 09h	/aemb/trunk/sim
53	Added GET/PUT support through a FSL bus.	sybreon	6115d 12h	/aemb/trunk/sim
52	Added log output to iverilog.log	sybreon	6115d 12h	/aemb/trunk/sim
50	Parameterised optional components.	sybreon	6116d 19h	/aemb/trunk/sim
49	Added random seed for simulation.	sybreon	6119d 22h	/aemb/trunk/sim
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6122d 14h	/aemb/trunk/sim
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6123d 06h	/aemb/trunk/sim
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6133d 14h	/aemb/trunk/sim
38	Added interrupt support.	sybreon	6278d 14h	/aemb/trunk/sim