URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk] - Rev 40

Rev	Log message	Author	Age	Path
20	Updated simulation scripts.	daniel.kho	3855d 17h	/axi4_tlm_bfm/trunk
19	Updated synthesis constraints and scripts.	daniel.kho	3855d 17h	/axi4_tlm_bfm/trunk
18	Added hardware PRBS generator, modularised top-level by having separate file as the tester.	daniel.kho	3855d 17h	/axi4_tlm_bfm/trunk
17	Added more pipelining, enhancements. Tested on BeMicro kit.	daniel.kho	3855d 17h	/axi4_tlm_bfm/trunk
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	3958d 14h	/axi4_tlm_bfm/trunk
15	[minor]: cleaned up sources.	daniel.kho	3960d 20h	/axi4_tlm_bfm/trunk
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	3969d 11h	/axi4_tlm_bfm/trunk
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	3969d 15h	/axi4_tlm_bfm/trunk
12	Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources.	daniel.kho	3978d 19h	/axi4_tlm_bfm/trunk
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	3980d 14h	/axi4_tlm_bfm/trunk