URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

Rev	Log message	Author	Age	Path
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7921d 10h	/can/tags/rel_11/rtl/verilog/can_bsp.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7922d 07h	/can/tags/rel_11/rtl/verilog/can_bsp.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7923d 00h	/can/tags/rel_11/rtl/verilog/can_bsp.v
26	Backup.	mohor	7927d 09h	/can/tags/rel_11/rtl/verilog/can_bsp.v
25	* empty log message *	mohor	7927d 11h	/can/tags/rel_11/rtl/verilog/can_bsp.v
24	backup.	mohor	7932d 01h	/can/tags/rel_11/rtl/verilog/can_bsp.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7946d 12h	/can/tags/rel_11/rtl/verilog/can_bsp.v
21	Data is stored to fifo at the end of ack stage.	mohor	7947d 04h	/can/tags/rel_11/rtl/verilog/can_bsp.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7947d 05h	/can/tags/rel_11/rtl/verilog/can_bsp.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7947d 11h	/can/tags/rel_11/rtl/verilog/can_bsp.v