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58 timescale.v is used for simulation only. mohor 7859d 02h /can/tags/rel_20
57 Mux used for clkout to avoid "gated clocks warning". mohor 7859d 02h /can/tags/rel_20
56 Doubled declarations removed. mohor 7860d 01h /can/tags/rel_20
55 wire declaration added. mohor 7860d 02h /can/tags/rel_20
53 CAN pins located. mohor 7865d 03h /can/tags/rel_20
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7865d 03h /can/tags/rel_20
51 Xilinx RAM added. mohor 7865d 04h /can/tags/rel_20
50 Top level signal names changed. mohor 7865d 04h /can/tags/rel_20
49 Actel APA ram changed. Now synchronous read is used. mohor 7868d 20h /can/tags/rel_20
48 Actel APA ram supported. mohor 7868d 20h /can/tags/rel_20

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