URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 61

Rev	Log message	Author	Age	Path
17	Addresses corrected to decimal values (previously hex).	mohor	7851d 02h	/can/tags/rel_9/bench/verilog/can_testbench.v
16	rx_fifo is now working.	mohor	7851d 07h	/can/tags/rel_9/bench/verilog/can_testbench.v
15	Temporary version (backup).	mohor	7855d 01h	/can/tags/rel_9/bench/verilog/can_testbench.v
14	rx fifo added. Not 100 % verified, yet.	mohor	7855d 21h	/can/tags/rel_9/bench/verilog/can_testbench.v
11	Acceptance filter added.	mohor	7857d 17h	/can/tags/rel_9/bench/verilog/can_testbench.v
10	Backup version.	mohor	7868d 15h	/can/tags/rel_9/bench/verilog/can_testbench.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7869d 19h	/can/tags/rel_9/bench/verilog/can_testbench.v
8	Testbench define file added. Clock divider register added.	mohor	7870d 03h	/can/tags/rel_9/bench/verilog/can_testbench.v
7	Tripple sampling supported.	mohor	7870d 17h	/can/tags/rel_9/bench/verilog/can_testbench.v
6	Commented lines removed.	mohor	7870d 19h	/can/tags/rel_9/bench/verilog/can_testbench.v