URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 96

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7556d 01h	/dbg_interface/tags/asyst_2
71	Mbist support added.	simons	7558d 07h	/dbg_interface/tags/asyst_2
70	A pdf copy of existing doc document.	simons	7565d 09h	/dbg_interface/tags/asyst_2
69	WBCNTL added, multiple CPU support described.	simons	7585d 22h	/dbg_interface/tags/asyst_2
67	Lower two address lines must be always zero.	simons	7591d 03h	/dbg_interface/tags/asyst_2
65	WB_CNTL register added, some syncronization fixes.	simons	7592d 02h	/dbg_interface/tags/asyst_2
63	Three more chains added for cpu debug access.	simons	7612d 03h	/dbg_interface/tags/asyst_2
61	Lapsus fixed.	simons	7640d 03h	/dbg_interface/tags/asyst_2
59	Reset value for riscsel register set to 1.	simons	7640d 03h	/dbg_interface/tags/asyst_2
57	Multiple cpu support added.	simons	7640d 05h	/dbg_interface/tags/asyst_2