URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl] - Rev 104

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7555d 13h	/dbg_interface/tags/asyst_2/rtl
71	Mbist support added.	simons	7557d 20h	/dbg_interface/tags/asyst_2/rtl
67	Lower two address lines must be always zero.	simons	7590d 16h	/dbg_interface/tags/asyst_2/rtl
65	WB_CNTL register added, some syncronization fixes.	simons	7591d 15h	/dbg_interface/tags/asyst_2/rtl
63	Three more chains added for cpu debug access.	simons	7611d 16h	/dbg_interface/tags/asyst_2/rtl
61	Lapsus fixed.	simons	7639d 16h	/dbg_interface/tags/asyst_2/rtl
59	Reset value for riscsel register set to 1.	simons	7639d 16h	/dbg_interface/tags/asyst_2/rtl
57	Multiple cpu support added.	simons	7639d 17h	/dbg_interface/tags/asyst_2/rtl
53	Trst active high. Inverted on higher layer.	mohor	7906d 15h	/dbg_interface/tags/asyst_2/rtl
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7906d 15h	/dbg_interface/tags/asyst_2/rtl