URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl] - Rev 46

Rev	Log message	Author	Age	Path
22	Register length fixed.	mohor	8267d 23h	/dbg_interface/tags/asyst_2/rtl
21	CRC is returned when chain selection data is transmitted.	mohor	8268d 19h	/dbg_interface/tags/asyst_2/rtl
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8269d 22h	/dbg_interface/tags/asyst_2/rtl
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8281d 22h	/dbg_interface/tags/asyst_2/rtl
18	Reset signals are not combined any more.	mohor	8284d 07h	/dbg_interface/tags/asyst_2/rtl
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8307d 21h	/dbg_interface/tags/asyst_2/rtl
15	bs_chain_o added.	mohor	8309d 22h	/dbg_interface/tags/asyst_2/rtl
13	Signal names changed to lowercase.	mohor	8310d 22h	/dbg_interface/tags/asyst_2/rtl
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8311d 23h	/dbg_interface/tags/asyst_2/rtl
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8332d 18h	/dbg_interface/tags/asyst_2/rtl