URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [bench] - Rev 115

Rev	Log message	Author	Age	Path
73	CRC logic changed.	mohor	7572d 20h	/dbg_interface/tags/highland_ver1/bench
63	Three more chains added for cpu debug access.	simons	7628d 22h	/dbg_interface/tags/highland_ver1/bench
47	mon_cntl_o signals that controls monitor mux added.	mohor	8106d 22h	/dbg_interface/tags/highland_ver1/bench
38	Few outputs for boundary scan chain added.	mohor	8162d 22h	/dbg_interface/tags/highland_ver1/bench
36	Structure changed. Hooks for jtag chain added.	mohor	8166d 21h	/dbg_interface/tags/highland_ver1/bench
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8307d 01h	/dbg_interface/tags/highland_ver1/bench
15	bs_chain_o added.	mohor	8309d 02h	/dbg_interface/tags/highland_ver1/bench
13	Signal names changed to lowercase.	mohor	8310d 02h	/dbg_interface/tags/highland_ver1/bench
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8311d 02h	/dbg_interface/tags/highland_ver1/bench
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8331d 22h	/dbg_interface/tags/highland_ver1/bench