URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

Rev	Log message	Author	Age	Path
43	Intentional error removed.	mohor	8126d 22h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8127d 00h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8163d 01h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8166d 20h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8196d 23h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8197d 22h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8197d 23h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8209d 03h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8245d 00h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v
25	trst signal is synchronized to wb_clk_i.	mohor	8259d 22h	/dbg_interface/tags/highland_ver1/rtl/verilog/dbg_top.v