URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [bench/] [verilog/] - Rev 158

Rev	Log message	Author	Age	Path
36	Structure changed. Hooks for jtag chain added.	mohor	8180d 00h	/dbg_interface/tags/rel_15/bench/verilog
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8320d 04h	/dbg_interface/tags/rel_15/bench/verilog
15	bs_chain_o added.	mohor	8322d 05h	/dbg_interface/tags/rel_15/bench/verilog
13	Signal names changed to lowercase.	mohor	8323d 06h	/dbg_interface/tags/rel_15/bench/verilog
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8324d 06h	/dbg_interface/tags/rel_15/bench/verilog
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8345d 02h	/dbg_interface/tags/rel_15/bench/verilog
9	Working version. Few bugs fixed, comments added.	mohor	8349d 06h	/dbg_interface/tags/rel_15/bench/verilog
6	Minor changes for simulation.	mohor	8350d 04h	/dbg_interface/tags/rel_15/bench/verilog
5	Trace fixed. Some registers changed, trace simplified.	mohor	8351d 02h	/dbg_interface/tags/rel_15/bench/verilog
2	Initial official release.	mohor	8356d 02h	/dbg_interface/tags/rel_15/bench/verilog