URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

Rev	Log message	Author	Age	Path
36	Structure changed. Hooks for jtag chain added.	mohor	8148d 12h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8178d 15h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8179d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8179d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8190d 19h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8226d 16h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
25	trst signal is synchronized to wb_clk_i.	mohor	8241d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
22	Register length fixed.	mohor	8248d 18h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
21	CRC is returned when chain selection data is transmitted.	mohor	8249d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8250d 16h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v