URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 116

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7595d 17h	/dbg_interface/tags/rel_19/bench
73	CRC logic changed.	mohor	7595d 17h	/dbg_interface/tags/rel_19/bench
63	Three more chains added for cpu debug access.	simons	7651d 20h	/dbg_interface/tags/rel_19/bench
47	mon_cntl_o signals that controls monitor mux added.	mohor	8129d 19h	/dbg_interface/tags/rel_19/bench
38	Few outputs for boundary scan chain added.	mohor	8185d 19h	/dbg_interface/tags/rel_19/bench
36	Structure changed. Hooks for jtag chain added.	mohor	8189d 18h	/dbg_interface/tags/rel_19/bench
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8329d 22h	/dbg_interface/tags/rel_19/bench
15	bs_chain_o added.	mohor	8331d 23h	/dbg_interface/tags/rel_19/bench
13	Signal names changed to lowercase.	mohor	8332d 23h	/dbg_interface/tags/rel_19/bench
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8334d 00h	/dbg_interface/tags/rel_19/bench