URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 121

Rev	Log message	Author	Age	Path
88	temp3 version.	mohor	7497d 20h	/dbg_interface/tags/rel_19/bench
87	tmp2 version.	mohor	7499d 01h	/dbg_interface/tags/rel_19/bench
80	New version of the debug interface. Not finished, yet.	mohor	7511d 23h	/dbg_interface/tags/rel_19/bench
75	Simulation files.	mohor	7572d 21h	/dbg_interface/tags/rel_19/bench
73	CRC logic changed.	mohor	7572d 21h	/dbg_interface/tags/rel_19/bench
63	Three more chains added for cpu debug access.	simons	7629d 00h	/dbg_interface/tags/rel_19/bench
47	mon_cntl_o signals that controls monitor mux added.	mohor	8106d 23h	/dbg_interface/tags/rel_19/bench
38	Few outputs for boundary scan chain added.	mohor	8162d 23h	/dbg_interface/tags/rel_19/bench
36	Structure changed. Hooks for jtag chain added.	mohor	8166d 22h	/dbg_interface/tags/rel_19/bench
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8307d 02h	/dbg_interface/tags/rel_19/bench