URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

Rev	Log message	Author	Age	Path
90	tmp version.	mohor	7504d 23h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
89	temp4 version.	mohor	7506d 05h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
88	temp3 version.	mohor	7507d 00h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
87	tmp2 version.	mohor	7508d 05h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
80	New version of the debug interface. Not finished, yet.	mohor	7521d 03h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
73	CRC logic changed.	mohor	7582d 01h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
63	Three more chains added for cpu debug access.	simons	7638d 03h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8116d 03h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
38	Few outputs for boundary scan chain added.	mohor	8172d 03h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v
36	Structure changed. Hooks for jtag chain added.	mohor	8176d 02h	/dbg_interface/tags/rel_19/bench/verilog/dbg_tb.v