URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog] - Rev 158

Rev	Log message	Author	Age	Path
91	tmp version.	mohor	7518d 18h	/dbg_interface/tags/rel_19/bench/verilog
90	tmp version.	mohor	7519d 13h	/dbg_interface/tags/rel_19/bench/verilog
89	temp4 version.	mohor	7520d 19h	/dbg_interface/tags/rel_19/bench/verilog
88	temp3 version.	mohor	7521d 14h	/dbg_interface/tags/rel_19/bench/verilog
87	tmp2 version.	mohor	7522d 19h	/dbg_interface/tags/rel_19/bench/verilog
80	New version of the debug interface. Not finished, yet.	mohor	7535d 17h	/dbg_interface/tags/rel_19/bench/verilog
75	Simulation files.	mohor	7596d 15h	/dbg_interface/tags/rel_19/bench/verilog
73	CRC logic changed.	mohor	7596d 15h	/dbg_interface/tags/rel_19/bench/verilog
63	Three more chains added for cpu debug access.	simons	7652d 17h	/dbg_interface/tags/rel_19/bench/verilog
47	mon_cntl_o signals that controls monitor mux added.	mohor	8130d 16h	/dbg_interface/tags/rel_19/bench/verilog