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[/] [dbg_interface/] [tags/] [rel_19] - Rev 93

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Rev Log message Author Age Path
69 WBCNTL added, multiple CPU support described. simons 7628d 16h /dbg_interface/tags/rel_19
67 Lower two address lines must be always zero. simons 7633d 21h /dbg_interface/tags/rel_19
65 WB_CNTL register added, some syncronization fixes. simons 7634d 20h /dbg_interface/tags/rel_19
63 Three more chains added for cpu debug access. simons 7654d 21h /dbg_interface/tags/rel_19
61 Lapsus fixed. simons 7682d 21h /dbg_interface/tags/rel_19
59 Reset value for riscsel register set to 1. simons 7682d 21h /dbg_interface/tags/rel_19
57 Multiple cpu support added. simons 7682d 22h /dbg_interface/tags/rel_19
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7949d 19h /dbg_interface/tags/rel_19
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7949d 19h /dbg_interface/tags/rel_19
53 Trst active high. Inverted on higher layer. mohor 7949d 20h /dbg_interface/tags/rel_19

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