URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Rev 102

Rev	Log message	Author	Age	Path
13	Signal names changed to lowercase.	mohor	8309d 14h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8310d 14h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8331d 10h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
9	Working version. Few bugs fixed, comments added.	mohor	8335d 14h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
6	Minor changes for simulation.	mohor	8336d 12h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8337d 10h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
2	Initial official release.	mohor	8342d 10h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v