URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

Rev	Log message	Author	Age	Path
91	tmp version.	mohor	7472d 01h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
90	tmp version.	mohor	7472d 20h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
89	temp4 version.	mohor	7474d 01h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
88	temp3 version.	mohor	7474d 20h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
87	tmp2 version.	mohor	7476d 01h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
80	New version of the debug interface. Not finished, yet.	mohor	7488d 23h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
73	CRC logic changed.	mohor	7549d 21h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
63	Three more chains added for cpu debug access.	simons	7606d 00h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8083d 23h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
38	Few outputs for boundary scan chain added.	mohor	8139d 23h	/dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v