URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench] - Rev 110

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8301d 21h	/dbg_interface/tags/rel_21/bench
15	bs_chain_o added.	mohor	8303d 22h	/dbg_interface/tags/rel_21/bench
13	Signal names changed to lowercase.	mohor	8304d 23h	/dbg_interface/tags/rel_21/bench
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8305d 23h	/dbg_interface/tags/rel_21/bench
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8326d 19h	/dbg_interface/tags/rel_21/bench
9	Working version. Few bugs fixed, comments added.	mohor	8330d 23h	/dbg_interface/tags/rel_21/bench
6	Minor changes for simulation.	mohor	8331d 21h	/dbg_interface/tags/rel_21/bench
5	Trace fixed. Some registers changed, trace simplified.	mohor	8332d 19h	/dbg_interface/tags/rel_21/bench
2	Initial official release.	mohor	8337d 19h	/dbg_interface/tags/rel_21/bench