URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

Rev	Log message	Author	Age	Path
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8263d 04h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8275d 05h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
18	Reset signals are not combined any more.	mohor	8277d 14h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8301d 03h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
15	bs_chain_o added.	mohor	8303d 04h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
13	Signal names changed to lowercase.	mohor	8304d 05h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8305d 05h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8326d 01h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
9	Working version. Few bugs fixed, comments added.	mohor	8330d 05h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v
8	Asynchronous set/reset not used in trace any more.	mohor	8331d 03h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_top.v