OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rev_23] - Rev 100

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 MBIST chain connection fixed. mohor 7601d 14h /dbg_interface/tags/rev_23
75 Simulation files. mohor 7601d 16h /dbg_interface/tags/rev_23
74 Removed. mohor 7601d 16h /dbg_interface/tags/rev_23
73 CRC logic changed. mohor 7601d 16h /dbg_interface/tags/rev_23
71 Mbist support added. simons 7603d 22h /dbg_interface/tags/rev_23
70 A pdf copy of existing doc document. simons 7611d 00h /dbg_interface/tags/rev_23
69 WBCNTL added, multiple CPU support described. simons 7631d 14h /dbg_interface/tags/rev_23
67 Lower two address lines must be always zero. simons 7636d 18h /dbg_interface/tags/rev_23
65 WB_CNTL register added, some syncronization fixes. simons 7637d 18h /dbg_interface/tags/rev_23
63 Three more chains added for cpu debug access. simons 7657d 18h /dbg_interface/tags/rev_23

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.