URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

Rev	Log message	Author	Age	Path
15	bs_chain_o added.	mohor	8295d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
13	Signal names changed to lowercase.	mohor	8296d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8297d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8318d 00h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
9	Working version. Few bugs fixed, comments added.	mohor	8322d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
8	Asynchronous set/reset not used in trace any more.	mohor	8323d 02h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8324d 00h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
2	Initial official release.	mohor	8329d 00h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v