URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl] - Rev 41

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8324d 15h	/dbg_interface/tags/sdram_test_working/rtl
15	bs_chain_o added.	mohor	8326d 16h	/dbg_interface/tags/sdram_test_working/rtl
13	Signal names changed to lowercase.	mohor	8327d 16h	/dbg_interface/tags/sdram_test_working/rtl
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8328d 16h	/dbg_interface/tags/sdram_test_working/rtl
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8349d 12h	/dbg_interface/tags/sdram_test_working/rtl
9	Working version. Few bugs fixed, comments added.	mohor	8353d 16h	/dbg_interface/tags/sdram_test_working/rtl
8	Asynchronous set/reset not used in trace any more.	mohor	8354d 14h	/dbg_interface/tags/sdram_test_working/rtl
5	Trace fixed. Some registers changed, trace simplified.	mohor	8355d 12h	/dbg_interface/tags/sdram_test_working/rtl
2	Initial official release.	mohor	8360d 12h	/dbg_interface/tags/sdram_test_working/rtl