URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl] - Rev 45

Rev	Log message	Author	Age	Path
21	CRC is returned when chain selection data is transmitted.	mohor	8320d 02h	/dbg_interface/tags/sdram_test_working/rtl
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8321d 05h	/dbg_interface/tags/sdram_test_working/rtl
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8333d 05h	/dbg_interface/tags/sdram_test_working/rtl
18	Reset signals are not combined any more.	mohor	8335d 14h	/dbg_interface/tags/sdram_test_working/rtl
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8359d 04h	/dbg_interface/tags/sdram_test_working/rtl
15	bs_chain_o added.	mohor	8361d 05h	/dbg_interface/tags/sdram_test_working/rtl
13	Signal names changed to lowercase.	mohor	8362d 05h	/dbg_interface/tags/sdram_test_working/rtl
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8363d 06h	/dbg_interface/tags/sdram_test_working/rtl
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8384d 01h	/dbg_interface/tags/sdram_test_working/rtl
9	Working version. Few bugs fixed, comments added.	mohor	8388d 05h	/dbg_interface/tags/sdram_test_working/rtl