URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working] - Rev 38

Rev	Log message	Author	Age	Path
18	Reset signals are not combined any more.	mohor	8312d 05h	/dbg_interface/tags/sdram_test_working
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8335d 19h	/dbg_interface/tags/sdram_test_working
16	bs_chain_o port added.	mohor	8337d 19h	/dbg_interface/tags/sdram_test_working
15	bs_chain_o added.	mohor	8337d 20h	/dbg_interface/tags/sdram_test_working
14	Document updated.	mohor	8338d 18h	/dbg_interface/tags/sdram_test_working
13	Signal names changed to lowercase.	mohor	8338d 20h	/dbg_interface/tags/sdram_test_working
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8339d 21h	/dbg_interface/tags/sdram_test_working
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8360d 17h	/dbg_interface/tags/sdram_test_working
10	First official release 1.0.	mohor	8364d 20h	/dbg_interface/tags/sdram_test_working
9	Working version. Few bugs fixed, comments added.	mohor	8364d 20h	/dbg_interface/tags/sdram_test_working