URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

Rev	Log message	Author	Age	Path
47	mon_cntl_o signals that controls monitor mux added.	mohor	8128d 21h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8143d 23h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8148d 22h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8149d 00h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8185d 01h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8188d 20h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8218d 23h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8219d 22h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8219d 23h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8231d 03h	/dbg_interface/trunk/rtl/verilog/dbg_top.v