URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [bench/] [verilog/] - Rev 361

Rev	Log message	Author	Age	Path
266	Flow control test almost finished.	mohor	7885d 12h	/ethmac/branches/unneback/bench/verilog
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7886d 03h	/ethmac/branches/unneback/bench/verilog
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7886d 15h	/ethmac/branches/unneback/bench/verilog
254	Temp version.	mohor	7888d 09h	/ethmac/branches/unneback/bench/verilog
252	Just some updates.	tadejm	7888d 12h	/ethmac/branches/unneback/bench/verilog
243	Late collision is not reported any more.	tadejm	7893d 16h	/ethmac/branches/unneback/bench/verilog
227	Changed BIST scan signals.	tadejm	7920d 12h	/ethmac/branches/unneback/bench/verilog
223	Some code changed due to bug fixes.	tadejm	7920d 15h	/ethmac/branches/unneback/bench/verilog
216	Bist signals added.	mohor	7927d 16h	/ethmac/branches/unneback/bench/verilog
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7929d 16h	/ethmac/branches/unneback/bench/verilog