URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [bench/] [verilog/] [tb_ethernet.v] - Rev 302

Rev	Log message	Author	Age	Path
179	Beautiful tests merget together	mohor	8000d 18h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
178	Rearanged testcases	mohor	8000d 18h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
177	Bug in MIIM fixed.	mohor	8000d 22h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
170	Headers changed.	mohor	8001d 00h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	8001d 01h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
158	Typo fixed.	mohor	8005d 20h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
156	Valid testbench.	mohor	8008d 01h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	8052d 20h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
117	Clock mrx_clk set to 2.5 MHz.	mohor	8056d 22h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	8056d 22h	/ethmac/branches/unneback/bench/verilog/tb_ethernet.v