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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Rev 351

Rev	Log message	Author	Age	Path
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7986d 01h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8067d 06h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8076d 08h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8112d 04h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8133d 00h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8143d 03h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8143d 04h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
55	Changed that were lost with last update put back to the file.	mohor	8144d 06h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8144d 20h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v
46	HASH0 and HASH1 registers added.	mohor	8147d 00h	/ethmac/branches/unneback/rtl/verilog/eth_defines.v