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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 134

Rev	Log message	Author	Age	Path
77	Interrupts changed	mohor	8127d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8138d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8138d 22h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8138d 22h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8139d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8141d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8143d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8145d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8147d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8148d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v