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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 115

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Rev Log message Author Age Path
91 Comments in Slovene language removed. mohor 8113d 02h /ethmac/tags/rel_14/rtl/verilog
90 casex changed with case, fifo reset changed. mohor 8113d 03h /ethmac/tags/rel_14/rtl/verilog
88 rx_fifo was not always cleared ok. Fixed. mohor 8122d 23h /ethmac/tags/rel_14/rtl/verilog
87 Status was not latched correctly sometimes. Fixed. mohor 8123d 01h /ethmac/tags/rel_14/rtl/verilog
86 Big Endian problem when sending frames fixed. mohor 8124d 08h /ethmac/tags/rel_14/rtl/verilog
85 Log info was missing. mohor 8129d 18h /ethmac/tags/rel_14/rtl/verilog
84 LinkFail signal was not latching appropriate bit. mohor 8129d 18h /ethmac/tags/rel_14/rtl/verilog
83 MAC address recognition was not correct (bytes swaped). mohor 8129d 18h /ethmac/tags/rel_14/rtl/verilog
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8129d 20h /ethmac/tags/rel_14/rtl/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8133d 22h /ethmac/tags/rel_14/rtl/verilog

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