URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 75

Rev	Log message	Author	Age	Path
53	Addition of new module eth_addrcheck.v	billditt	8145d 13h	/ethmac/tags/rel_14/rtl/verilog
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8145d 14h	/ethmac/tags/rel_14/rtl/verilog
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8145d 15h	/ethmac/tags/rel_14/rtl/verilog
48	RxOverRun added to statuses.	mohor	8147d 17h	/ethmac/tags/rel_14/rtl/verilog
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8147d 17h	/ethmac/tags/rel_14/rtl/verilog
46	HASH0 and HASH1 registers added.	mohor	8147d 17h	/ethmac/tags/rel_14/rtl/verilog
43	Tx status is written back to the BD.	mohor	8149d 01h	/ethmac/tags/rel_14/rtl/verilog
42	Rx status is written back to the BD.	mohor	8151d 18h	/ethmac/tags/rel_14/rtl/verilog
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8153d 20h	/ethmac/tags/rel_14/rtl/verilog
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8154d 17h	/ethmac/tags/rel_14/rtl/verilog