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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 344

Rev	Log message	Author	Age	Path
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	8030d 04h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8050d 05h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8052d 08h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	8055d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8057d 07h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	8064d 20h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8065d 10h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	8065d 23h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	8066d 03h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8133d 13h	/ethmac/tags/rel_14/rtl/verilog/eth_wishbone.v