URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 221

Rev	Log message	Author	Age	Path
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8120d 21h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8127d 01h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8127d 01h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8136d 22h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8137d 00h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8138d 07h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8143d 18h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8147d 21h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8147d 21h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8158d 21h	/ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v