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[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 221

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96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8117d 22h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8124d 01h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8124d 01h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8133d 22h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8134d 00h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8135d 07h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8140d 19h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8144d 21h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8144d 21h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8155d 21h /ethmac/tags/rel_15/rtl/verilog/eth_wishbone.v

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