URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 159

Rev	Log message	Author	Age	Path
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8163d 14h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8167d 16h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8167d 16h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8178d 16h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8178d 20h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8178d 21h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8179d 12h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8181d 16h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8182d 23h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8185d 16h	/ethmac/tags/rel_16/rtl/verilog/eth_wishbone.v