URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog] - Rev 259

Rev	Log message	Author	Age	Path
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7914d 01h	/ethmac/tags/rel_17/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7917d 02h	/ethmac/tags/rel_17/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7917d 04h	/ethmac/tags/rel_17/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7918d 01h	/ethmac/tags/rel_17/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7918d 01h	/ethmac/tags/rel_17/rtl/verilog
212	Minor $display change.	mohor	7918d 01h	/ethmac/tags/rel_17/rtl/verilog
211	Bist added.	mohor	7918d 01h	/ethmac/tags/rel_17/rtl/verilog
210	BIST added.	mohor	7918d 01h	/ethmac/tags/rel_17/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7934d 23h	/ethmac/tags/rel_17/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7934d 23h	/ethmac/tags/rel_17/rtl/verilog