URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 105

Rev	Log message	Author	Age	Path
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8166d 01h	/ethmac/tags/rel_19/rtl/verilog
80	Small fixes for external/internal DMA missmatches.	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
79	RetryCntLatched was unused and removed from design	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
78	WB_SEL_I was unused and removed from design	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
77	Interrupts changed	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
76	Interrupts changed in the top file	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
75	r_Bro is used for accepting/denying frames	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
74	Reset values are passed to registers through parameters	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
73	Number of interrupts changed	mohor	8170d 04h	/ethmac/tags/rel_19/rtl/verilog
72	Retry is not activated when a Tx Underrun occured	mohor	8174d 08h	/ethmac/tags/rel_19/rtl/verilog