URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 363

Rev	Log message	Author	Age	Path
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8133d 19h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8137d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8137d 22h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8148d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8149d 02h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8149d 02h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8149d 17h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8151d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8153d 05h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8155d 22h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v