URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_21/] [rtl/] [verilog/] - Rev 277

Rev	Log message	Author	Age	Path
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7895d 00h	/ethmac/tags/rel_21/rtl/verilog
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7895d 00h	/ethmac/tags/rel_21/rtl/verilog
238	Defines fixed to use generic RAM by default.	mohor	7907d 04h	/ethmac/tags/rel_21/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7909d 10h	/ethmac/tags/rel_21/rtl/verilog
232	fpga define added.	mohor	7915d 04h	/ethmac/tags/rel_21/rtl/verilog
229	case changed to casex.	mohor	7921d 02h	/ethmac/tags/rel_21/rtl/verilog
227	Changed BIST scan signals.	tadejm	7921d 06h	/ethmac/tags/rel_21/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7921d 07h	/ethmac/tags/rel_21/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7925d 07h	/ethmac/tags/rel_21/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7928d 07h	/ethmac/tags/rel_21/rtl/verilog