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[/] [ethmac/] [tags/] [rel_21/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 278

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7989d 16h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7991d 19h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7995d 10h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7996d 18h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	8004d 08h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8004d 21h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	8005d 11h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	8005d 14h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8073d 00h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8082d 02h	/ethmac/tags/rel_21/rtl/verilog/eth_wishbone.v