URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] [eth_top.v] - Rev 363

Rev	Log message	Author	Age	Path
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7939d 11h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7947d 14h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
164	Ethernet debug registers removed.	mohor	7949d 18h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7950d 16h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7955d 10h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7996d 10h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8004d 10h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8079d 18h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8090d 14h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8118d 15h	/ethmac/tags/rel_24/rtl/verilog/eth_top.v