URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] - Rev 275

Rev	Log message	Author	Age	Path
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7883d 01h	/ethmac/tags/rel_26
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7883d 02h	/ethmac/tags/rel_26
248	wb_rst_i is used for MIIM reset.	mohor	7884d 02h	/ethmac/tags/rel_26
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7887d 05h	/ethmac/tags/rel_26
245	Rev 1.7.	mohor	7887d 22h	/ethmac/tags/rel_26
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7888d 00h	/ethmac/tags/rel_26
243	Late collision is not reported any more.	tadejm	7888d 06h	/ethmac/tags/rel_26
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7888d 21h	/ethmac/tags/rel_26
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7888d 21h	/ethmac/tags/rel_26
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7888d 21h	/ethmac/tags/rel_26