URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27] - Rev 155

Rev	Log message	Author	Age	Path
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	8003d 23h	/ethmac/tags/rel_27
131	LinkFail signal was not latching appropriate bit.	mohor	8003d 23h	/ethmac/tags/rel_27
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	8004d 00h	/ethmac/tags/rel_27
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	8004d 01h	/ethmac/tags/rel_27
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8023d 23h	/ethmac/tags/rel_27
126	InvalidSymbol generation changed.	mohor	8023d 23h	/ethmac/tags/rel_27
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	8024d 00h	/ethmac/tags/rel_27
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	8024d 00h	/ethmac/tags/rel_27
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8026d 01h	/ethmac/tags/rel_27
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	8026d 01h	/ethmac/tags/rel_27