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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 192

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Rev Log message Author Age Path
108 Testbench supports unaligned accesses. mohor 8069d 10h /ethmac/trunk/bench/verilog
107 TX_BUF_BASE changed. mohor 8069d 10h /ethmac/trunk/bench/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8114d 08h /ethmac/trunk/bench/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8135d 04h /ethmac/trunk/bench/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8145d 08h /ethmac/trunk/bench/verilog
66 Testbench fixed, code simplified, unused signals removed. mohor 8145d 13h /ethmac/trunk/bench/verilog
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8147d 00h /ethmac/trunk/bench/verilog
49 HASH0 and HASH1 register read/write added. mohor 8149d 00h /ethmac/trunk/bench/verilog
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8155d 06h /ethmac/trunk/bench/verilog
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8215d 08h /ethmac/trunk/bench/verilog

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