URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 347

Rev	Log message	Author	Age	Path
69	Define missmatch fixed.	mohor	8141d 05h	/ethmac/trunk/rtl/verilog/eth_registers.v
68	Registered trimmed. Unused registers removed.	mohor	8142d 04h	/ethmac/trunk/rtl/verilog/eth_registers.v
56	File format fixed a bit.	mohor	8143d 07h	/ethmac/trunk/rtl/verilog/eth_registers.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8143d 22h	/ethmac/trunk/rtl/verilog/eth_registers.v
46	HASH0 and HASH1 registers added.	mohor	8146d 01h	/ethmac/trunk/rtl/verilog/eth_registers.v
37	Link in the header changed.	mohor	8166d 08h	/ethmac/trunk/rtl/verilog/eth_registers.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8215d 03h	/ethmac/trunk/rtl/verilog/eth_registers.v
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8215d 08h	/ethmac/trunk/rtl/verilog/eth_registers.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8262d 10h	/ethmac/trunk/rtl/verilog/eth_registers.v
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8263d 06h	/ethmac/trunk/rtl/verilog/eth_registers.v