OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 227

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 RxAbort is connected differently. mohor 8151d 03h /ethmac/trunk/rtl/verilog/ethmac.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8151d 05h /ethmac/trunk/rtl/verilog/ethmac.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8151d 20h /ethmac/trunk/rtl/verilog/ethmac.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 8153d 23h /ethmac/trunk/rtl/verilog/ethmac.v
43 Tx status is written back to the BD. mohor 8155d 07h /ethmac/trunk/rtl/verilog/ethmac.v
42 Rx status is written back to the BD. mohor 8158d 00h /ethmac/trunk/rtl/verilog/ethmac.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8160d 02h /ethmac/trunk/rtl/verilog/ethmac.v
37 Link in the header changed. mohor 8174d 06h /ethmac/trunk/rtl/verilog/ethmac.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8223d 01h /ethmac/trunk/rtl/verilog/ethmac.v
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8223d 06h /ethmac/trunk/rtl/verilog/ethmac.v

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.